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International Journal
of Computer Engineering in Research Trends (IJCERT)

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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

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Design of DC-DC Boost Converter in CMOS 0.18µm Technology

Gayatri Vidya Parishad College of Engineering for Women, Visakhapatnam, Andhra Pradesh, India.

A CMOS DC-DC boost converter with fastest settling time and less quiescent current with a feedback control is implemented. An extra path is introduced because of an error amplifier (OTA) which has an effective control for fast response. Efficient compensation with soft-start is used to make the quiescent current low. An on-chip current sensing circuit is introduced with less number of I/O pins for current mode control. In this project, the DC-DC boost converter is designed in Cadence virtuoso 0.18µm technology with a 5V supply. With a wide range of loads, it provides 25V at the output, 50mA load current with 90% efficiency. The circuit is operated at 500 KHz clock frequency with output ripple voltage of 20mV by using 4.7µF off-chip capacitor and 75µH off-chip inductor.

M.Rama Devi et al. ," Design of DC-DC Boost Converter in CMOS 0.18µm Technology”, International Journal of Computer Engineering In Research Trends, 3(10):554-560,October-2016.

Keywords : DC-DC Boost converter, operational Tran’s conductance amplifier (OTA), comparator, pulse width generator, compensator, current sensing circuit, oscillator and ramp generator circuit

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