Area Efficient and High Speed Vedic Multiplier Using Different Compressors
RAJARAPU KRISHNANJANEYULU, Y.KONDAIAH, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssociate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
The performance of trending technology in VLSI field supports ongoing expectation for high speed
Processing and lower area consumption. It is also a well known fact that the multiplier unit forms an integral part of
processor design. Due to this regard, high speed multiplier architectures become the need of the day. The proposed design
has reduced area, LUT tables and increase the speeds compared with the regular compressor based multiplier. The
multiplication sutra between these 16 sutras is the Urdhva Tiryakbhayam sutra which means vertical and crosswise. In this
paper it is used for designing a high speed, low power 4*4 multiplier. The proposed system is design using VHDL and it is
implemented through Xilinx ISE 14.2. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA
and the timing and area of the design, on the same have been calculated.
RAJARAPU KRISHNANJANEYULU,Y.KONDAIAH."Area Efficient and High Speed Vedic Multiplier Using Different Compressors". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.875-880, October- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1016.pdf,
Keywords : Ripple Carry Adder, half adder, full adder, Compressors, high speed multiplier, Urdhwa Tiryakbhyam Sutra,
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