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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Open Access and Multidisciplinary

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Implementation of Double Precision Floating Point Multiplier in VHDL

SUNKARA YAMUNA RANI, BELLAM VARALAKSHMI, , ,
Affiliations
(M.Tech) VLSI, Dept. of ECE
Assistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
:NOT ASSIGNED


Abstract
Floating point arithmetic is widely used in many areas. IEEE Standard 754 floating point is the most common representation today for real numbers on computers. IEEE standards specify a set of floating point formats for single precision and double precision. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. FPGAs are generally slower than their application specific integrated circuit (ASIC) counterparts, as they can't handle as complex a design, and draw more power. However, they have several advantages such as a shorter time to market, ability to re-program in the field to fix bugs, and lower nonrecurring engineering cost costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. Double precision floating point multiplier using three stage pipelining technique achieved the maximum frequency of 489.045 MHz with minimum delay 2.045 ns and area of 888 slices. Double precision FPM targeted on a Xilinx Virtex-6 xc6vlx75t-3ff484 device. This pipelined floating point multiplier performs the rounding operation and also handles various exceptions conditions. The double precision floating point multiplier was simulated in ISE simulator and synthesized using Xilinx ISE 13.2 tool. Key Words: Single Precision


Citation
SUNKARA YAMUNA RANI,BELLAM VARALAKSHMI."Implementation of Double Precision Floating Point Multiplier in VHDL". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 10,pp.881-888, October- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1017.pdf,


Keywords : Double precision, floating point, adder/subtractor, multiplier, FPGA, IEEE-754, Virtex-6

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DOI:10.22362/ijcert


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