Design and Simulation of High Speed Low Power CMOS Comparator
A.Rajeswari, T.Venkatarao, , ,
Affiliations (M.Tech) DECS Branch, Department of ECEAsst.Professor, Department of ECE Vignan's Nirula Iinstitute of Technology & Science for Women Pedapalakaluru, Guntur, Andhra Pradesh, India
In high-speed high-resolution analog to digital converters, comparators have a key role in quality of
performance. High power consumption and delay is one of the drawbacks of these circuits which can be reduced by using
suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep submicron design technologies. Back to-back inverter in the latch stage is replaced with dual-input single output differential
amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power
dissipation and higher speed than the conventional comparators. The circuit is simulated with 0.8V DC supply voltage and
250 MHz clock frequency. The proposed circuit analyses the Inverter based differential amplifier design compared to
double tail comparator is a less delay and controls the power dissipation. Finally output results shown by using T-Spice tool
A.Rajeswari,T.Venkatarao."Design and Simulation of High Speed Low Power CMOS Comparator". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.699-704, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1101.pdf,
Keywords : CMOS comparator, low power, High Speed, Analog-to-Digital Converter and Tanner EDA tool
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