DRAM based on Self Controllable Voltage Level Technique for Leakage Power in VLSI
M S V D RAJU KUNAPAREDDY, Y.KONDAIAH, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssociate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
Today trend is circuit characterized by reliability, low power dissipation, low leakage current, low cost and
there is required to reduce each of these. Increase of chip complexity is consistently higher for memory circuits. The salient
features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and low
leakage current, most of these have get give a better advantage. Power must be added to the portable unit, even when
power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that
methodologies for the design of high-throughput, low-power digital systems are needed. Since there is no additional
circuitry needed for power reduction in this circuit design technique, there is no additional circuitry needed for power
reduction Here 3T DRAM is implementing with self controllable voltage level (svl) technique is for reducing leakage current
in 0.12um technology. The simulation is done by using microwind 3.1 & dsch2 and gives the advantage of reducing the
leakage current up to 57%.
M S V D RAJU KUNAPAREDDY,Y.KONDAIAH."DRAM based on Self Controllable Voltage Level Technique for Leakage Power in VLSI". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.847-856, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1129.pdf,
Keywords : low leakage power, high performance, self controllable voltage level technique, low cost, low power
1. Frangois Odiot, Hugues Brut, “New Test Structure For High Resozution Leakage Current And Capacitance Measurements In CMOS Imager Appncations,” Proc. 1EEE 2004 Int. Conference On Microelectronic Test Structures, Vol 17, March 2004.
2. Satoshi Kurihara, Yanuar Z. Arief, Takumi Tsurusaki, Shinya Ohtsuka, “Construction Of Remote Monitoring System For Separative Measurement Of Leakage Current Of Outdoor Insulators,” Proceedings Of The 7th Lntemarional Conference On Properties And Applications Of Dielectric Materials June 1-5 2003 Nagoya.
3. Rajeev Rao, Student Member, IEEE, Ashish Srivastava, Student Member, IEEE, David Blaauw, Member, IEEE, And Dennis Sylvester, Member, IEEE, ” Statistical Analysis Of Subthreshold Leakage Current For VLSI Circuits,’’ Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 12, No. 2, February 2004.
4. F. Meghnefi, C. Volat And M. Farzaneh, “Temporal And Frequency Analysis Of The Leakage Current Of A Station Post Insulator During Ice Accretion,” IEEE Transactions On Dielectrics And Electrical Insulation Vol. 14, No. 6; December 2007.
5. Lin Yuan and Gang Qu, “A Combined Gate Replacement Reduction,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 14, No. 2, February 2006.
6. Soo Han Choi, Young Hee Park, Chul Hong Park, Sang Hoon Lee, Moon Hyun Yoo1, “Efficient Characterization And Suppression Methodology Of Edge Effects For Leakage Current Reduction Of Sub40nm DRAM Device,” IEEE International Conference On Microelectronic Test Structures, March 22-25, Hiroshima, Japan 2010.
7. Dongwoo Lee, Student Member, IEEE, David Blaauw, Member, IEEE, And Dennis Sylvester, Member, IEEE, “Gate Oxide Leakage Current Analysis And Reduction For VLSI Circuits,” IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 12, No. 2, February 2004 .
8. N. H. E. Weste, And K. Eshraghian, Editor.“Principles Of Cmos Vlsi Design”, A Systems Perspective, 2nd Ed. Addison-Wesley, 1993.
9. Chao-Chi Hong, Chang-Yun Chang, Chaung-Yuan Lee, And Jenn-Gwo Hwu, Senior Member, IEEE, “Reduction In Leakage Current Of Low-Temperature Thin-Gate Oxide By Repeated Spike Oxidation Technique,” IEEE Electron Device Letters, Vol. 23, No. 1, January 2002.
10. Yutaka Kobayashi, Kyoichiro Asayama, Masayuki Oohayashi, Ryoichi Hori, Goro Kitsukawa, And Kiyoo Itoh, “Bipolar Cmos-Merged Technology For A HighSpeed 1 - Mbit Dram,” IEEE Transactions On Electron Devices, Vol. 36, No. 4. April 1989.
11. Pavan.T.K. Jagannadha Naidu.K Shekar Babu.M,” Implementation Of Delay And Power Monitoring Schemes To Reduce The Power Consumption, Proceedings Of 2011 International Conference On Signal Processing, Communication, Computing And Networking Technologies (ICSCCN 2011).
12. Mohammad Sharifkhani, Member, IEEE, And Manoj Sachdev, Senior Member, IEEE, “Segmented Virtual Ground Architecture For Low-Power Embedded SRAM, IEEE Transactions On Very Large Scale Integration Systems, Vol.