Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
The full Adder is designed using CMOS logic style by dividing it in three modules so that it can be optimized
at various levels. First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs
simultaneously and have a good driving capability. The main motive is to determine the comparison of power, surface area
and complexity of Full adder designs using CMOS Logic Styles. Logic style affects the switching capacitance, transition
activity, short circuit current and delay. Various logic styles have been compared taking full adder as a reference circuit
and power dissipation and delay as reference parameters. Full adder Design is better compared to conventional design.
Transistor Design with respect to power, delay, Power Delay Product Comparison. It is observed that less power is
consumed in the Transmission based full adder than the Convention full adder and Pass Transistor full adder.
MUDRABOYINA SRINIVASA RAO,BELLAM VARALAKSHMI."Performance Analysis of High Speed CMOS Full Adder Circuits For Embedded System". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.857-861, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1130.pdf,
Keywords : CMOS logic style, full adder, high speed, low power.
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