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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Open Access and Multidisciplinary

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ASIC Design of Reversible Full Adder and Multiplier Circuits

CHADARASUPALLI NAGA LAKSHMI, P T BALAKRISHNA, , ,
Affiliations
(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women
:NOT ASSIGNED


Abstract
Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nano-computing and optical computing. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In this paper we propose a new 4×4 universal reversible logic gate. The proposed reversible gate can be used to synthesize any given Boolean functions. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. In this paper we have used Peres gate and the proposed Modified HNG (MHNG) gate to construct the reversible fault tolerant multiplier circuit


Citation
CHADARASUPALLI NAGA LAKSHMI,P T BALAKRISHNA."ASIC Design of Reversible Full Adder and Multiplier Circuits". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.882-886, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1135.pdf,


Keywords : Reversible logic, Garbage output, Garbage constant, Quantum Cost

References
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DOI:10.22362/ijcert


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