ASIC Design of Reversible Full Adder and Multiplier Circuits
CHADARASUPALLI NAGA LAKSHMI, P T BALAKRISHNA, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssociate Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women
Reversible logic has become one of the most promising research areas in the past few decades and has
found its applications in several technologies; such as low power CMOS, nano-computing and optical computing. The
problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In this paper we
propose a new 4×4 universal reversible logic gate. The proposed reversible gate can be used to synthesize any given
Boolean functions. We also gain better improvements in terms of power and area when compared to conventional adders
and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. We also gain
better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented
designs are simulated using NC launch and synthesized by RTL compiler. In this paper we have used Peres gate and the
proposed Modified HNG (MHNG) gate to construct the reversible fault tolerant multiplier circuit
CHADARASUPALLI NAGA LAKSHMI,P T BALAKRISHNA."ASIC Design of Reversible Full Adder and Multiplier Circuits". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 11,pp.882-886, November- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1135.pdf,
 R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM Journal of Research and Development, 5, pp. 183-191, 1961.
 Prashanth.N.G, Savitha.A.P, M.B.Anandaraju, Nuthan.A.C Design and Synthesis of Fault Tolerant Full Adder/Subtractor Using Reversible Logic Gates (IJERA) Vol. 3, Issue 4, Jul-Aug 2013.
 Adders Md. Saiful Islam, Muhammad Mahbubur Rahman, Zerina begum, and Mohd. Zulfiquar Hafiz. Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip
 Ko-ChiKuon, Chi-WenChou Low power and high speed multiplier design with row by passing and parallel architecture, Microelectronics Journal41 (2010).
 Yvav van Rentergem and Alexis De Vos Optimal Design of a Reversible Full Adder. 17 December 2004.
 Manjeet Singh Sankhwar , Rajesh Khatri Int Design of High Speed Low Power Reversible Logic Adder Using HNG Gate. Journal of Engineering Research and Applications Vol. 4, Issue 1 January 2014.
 Md.Belayet Alli,Md.samlur Rahman,Thmina Parvin ,optimized design of carry skip BCD adder using new FHNG Reversible logic gates (IJCS) july 2012.
 P. Moallema, M. Ehsanpour ,A Novel Design of Reversible Multiplier Circuit June 2013.
 Himanshu Thapliyal and M.B Srinivas, Novel Reversible Multiplier Architecture Using Reversible TSG Gate.
 Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas,Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
 Md. Saiful Islam, A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology.
 J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, and X. Li. Efficient Adder Circuits Based on a Conservative Reversible Logic Gate.
 Parisa Safari , Majid Haghparast , Asgar Azari,A Design of Fault Tolerant Reversible Arithmetic Logic Unit,Life Science Journal 2012.
 Stephen Brown, Zvonko Vranesic, et al.” Fundamentals of Digital Logic with Verilog Design” The McGraw-Hill Companies, Second Edition.
 H. Thapliyal and N. Ranganathan, "Design of Efficient Reversible Binary Subtractions Based on New Reversible Gate," Proc. of the I Computer Society Annual Symposium on VLSI, 2009
We have kept IJCERT is a free peer-reviewed scientific journal to endorse conservation. We have not put up a paywall to readers, and we do not charge for publishing. But running a monthly journal costs is a lot. While we do have some associates, we still need support to keep the journal flourishing. If our readers help fund it, our future will be more secure.