Impact Factor:6.549
 Scopus Suggested Journal: Tracking ID for this title suggestion is: 55EC484EE39417F0

International Journal
of Computer Engineering in Research Trends (IJCERT)

Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary




Welcome to IJCERT

International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

ISSN(Online):2349-7084                 Submit Paper    Check Paper Status    Conference Proposal

Back to Current Issues

Design and implementation of high speed 8 bit Vedic multiplier on FPGA

ANNAM ARAVIND KUMAR, SK. MASTAN BASHA, , ,
Affiliations
(M.Tech) VLSI, Dept. of ECE
Assistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
:NOT ASSIGNED


Abstract
In high speed digital signal processing units arithmetic logic units, multiplier and accumulate units, the multipliers are use as the key block. A systems performance is generally determined by the speed of the multiplier since multiplier is one of the key hardware component in high performance systems such as FIR filters, digital signal processors and microprocessors etc. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. With the increasing constraints on delay, more and more emphasis is being laid on design of faster multiplications. The Array multiplier, Vedic 4*4 multiplier and 8*8 multiplier are designed, then 16*16 multiplier. These adders are called compressors. Amongst these Vedic multipliers based on Vedic mathematics are presently under focus due to these being one of the fastest and low power multiplier. In this paper a 4 X 4 Vedic multiplier is designed using reversible logic gates which is efficient in terms of constant inputs, garbage outputs, quantum cost, area, speed and power. The design is simulated using Verilog. Compressor based Vedic Multipliers show considerable improvements in speed and area efficiency over the conventional ones.


Citation
ANNAM ARAVIND KUMAR,SK. MASTAN BASHA."Design and implementation of high speed 8 bit Vedic multiplier on FPGA". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1062-1069, December- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1244.pdf,


Keywords : Multiplier, Vedic multiplier, Reversible logic, garbage output, quantum cost.

References
[1] Swami Bharati Krsna Tirtha, Vedic Mathematics. Delhi: Motilal Banarsidass publishers 1965 
[2] Rakshith Saligram and Rakshith T.R. "Design of Reversible Multipliers for linear filtering Applications in DSP" International Journal of VLSI Design and Communication systems, Dec-12 
[3] R. Landauer,"Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp.183-191, 1961. 
[4] C.H. Bennett, "Logical reversibility of Computation", IBM J. Research and Development, pp.525-532, November 1973. 
[5] R. Feynman, "Quantum Mechanical Computers," Optics News,Vol.1l, pp. 11-20, 1985. 
[6] H. Thapliyal and M.B. Srinivas, "Novel Reversible Multiplier Architecture Using Reversible TSG Gate", Proc. IEEE International Conference on Computer Systems and Applications, pp. 100-103, March 20 06. 
[7] Shams, M., M. Haghparast and K. Navi, Novel reversible multiplier circuit in nanotechnology. World Appl. Sci. J.,3(5): 806-810. 
[8] Somayeh Babazadeh and Majid Haghparast, "Design of a Nanometric Fault Tolerant Reversible Multiplier Circuit" Journal of Basic and Applied Scientific Research, 2012. 
[9] Thapliyal, H., M.B. Srinivas and H.R. Arabnia, 2005, A Reversible Version of 4x4 Bit Array Multiplier with Minimum Gates and Garbage Outputs, Int. Conf. Embedded System, Applications (ESA'05), Las Vegas, USA, pp: 106 114. 
[10] H. Thapliyal and M.B. Srinivas, "Reversible Multiplier Architecture Using TSG Gate", Proc. IEEE International Conference on Computer Systems and Applications, pp. 241- 244, March 20 07.
 [11] M. Haghparast et al. , "Design of a Novel Reversible Multiplier Circuit using HNG Gate in Nanotechnology," in World Applied Science Journal, Vol. 3, No. 6, pp. 974-978, 2008. 
[12] M. S. Islam et al. , "Realization of Reversible Multiplier Circuit," in Information Tech. 1, Vol. 8, No. 2, pp. 117-121, 2005. 
[13] K. Navi, M. Haghparast, S. JafaraliJassbi, O. Hashemipour, Design of a novel reversible multiplier circuit using HNG gate, World Sci. 1 3 (6). 
[14] M. Shams et al., "Novel Reversible Multiplier Circuits in Nanotechnology," in World Applied Science Journal, Vol. 3, No. 5, pp, pp. 806- 810, 2008. 
[15] M S Islam, M M Rahman, Z Begum and M Z Hafiz, 2009. Low Cost Quantum Realization of Reversible Multiplier Circuit. Information Technology Journal, vol. 8(2), pp. 208-213.


DOI Link : NOT ASSIGNED

Download :
  V2I1244.pdf


Refbacks : Currently there are no Refbacks

Support Us


We have kept IJCERT is a free peer-reviewed scientific journal to endorse conservation. We have not put up a paywall to readers, and we do not charge for publishing. But running a monthly journal costs is a lot. While we do have some associates, we still need support to keep the journal flourishing. If our readers help fund it, our future will be more secure.

Quick Links



DOI:10.22362/ijcert


Science Central

Score: 13.30





Submit your paper to editorijcert@gmail.com