FPGA Based Efficient Implementation of Viterbi Decoder
BEERAM RAJ MOHAN REDDY, BELLAM VARALAKSHMI, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
Convolutional encoding is a forward error correction technique that is used for correction of errors at the
receiver end. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In
this paper, we present a Spartan XC3S400A Field- Programmable Gate Array efficient implementation of Viterbi Decoder
with a constraint length of 3 and a code rate of 1/3. The proposed architecture can be realized by an Adaptive Viterbi
Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2 using Verilog HDL. Simulation is done using Xilinx
ISE 12.4i design software and it is targeted into Xilinx Virtex-5, XC5VLX110T FPGA. The parameters of Viterbi algorithm
can be changed to suit a specific application. The high speed and small area are two important design parameters in
today’s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using track back
architecture and embedded BRAM of target FPGA. It shows that the larger the constraint length used in a convolutional
encoding process, the more powerful the code produced.
BEERAM RAJ MOHAN REDDY,BELLAM VARALAKSHMI."FPGA Based Efficient Implementation of Viterbi Decoder". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1076-1082, December- 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1246.pdf,
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