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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Open Access and Multidisciplinary

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IMPLEMENTATION OF HARDWARE IP ROUTER BASED ON VLSI

KARLAPUDI SRAVANI, P T BALAKRISHNA, , ,
Affiliations
(M.Tech) VLSI, Dept. of ECE
Associate Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women
:NOT ASSIGNED


Abstract
A Network-on-chip is a new paradigm in complex system-on-chip designs that provide efficient on chip communication networks. It allows scalable communication and allows decoupling of communication and computation. The data is routed through the networks in terms of packets. We attempts to overcome latency and time reduction issue and can provide multipurpose networking router by means of verilog and it was synthesized in Xilinx 13.2 version, simulated Modelsim 10.0 version. In this paper our attempt is to provide a multipurpose networking router by means of Verilog code, by this we can maintain the same switching speed with more secured way of approach we have even the packet storage buffer on chip being generated by code in our design in the so we call this as the self-independent router called as the VLSI Based router. The three architectures were analyzed for their performance in terms of delay, throughput and latency and we concluded that CDMA router performs better than the other two.


Citation
KARLAPUDI SRAVANI,P T BALAKRISHNA."IMPLEMENTATION OF HARDWARE IP ROUTER BASED ON VLSI". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1222-1227, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1275.pdf,


Keywords : Fictional Coverage, assertions, Randomization, Network-On-Chip,, Register blocks.

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DOI:10.22362/ijcert


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