Investigation on Performance of high speed CMOS Full adder Circuits
KATTUPALLI KALYANI, G.VASANTH RAO, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssistant Professor, Dept. of ECE Priyadarshini Institute of Technology & Science for Women
- In this paper we demonstrate the performance analysis of CMOS Full adder circuits in this connection the
full Adder is designed using CMOS logic style by dividing it in three modules so that it can be optimized at various levels.
First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a
good driving capability. The objective this concept is identified the comparison of power, surface area and complexity of
Full adder designs using CMOS Logic Styles. Full adder Design is better compared to conventional design. Transistor
Design with respect to power, delay, Power Delay Product Comparison. It is observed that less power is consumed in the
Transmission based full adder than the Convention full adder and Pass Transistor full adder.
KATTUPALLI KALYANI,G.VASANTH RAO."Investigation on Performance of high speed CMOS Full adder Circuits ". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1228-1231, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1276.pdf,
Keywords : High speed, low power. CMOS logic style, full adder.
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