SYSTEM EVALUATION OF 32 BIT UNNSIGNED MULTIPLER USING CLAA AND CSLA.
SIVASANKAR RAO.Y, SOMASEKHAR .A, , ,
Affiliations (M.Tech) VLSI, Dept. of ECEAssociate Professor, Dept. of ECE Priyadarshini Institute of Technology & Management
- In this paper deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-
bit signed and unsigned integer multiplier. Multiplication is a fundamental operation in most signal processing algorithms.
Multipliers have large area, long latency and consume considerable power. Therefore low-power multiplier design has
been an important part in low- power VLSI system design. In computational circuits the adders plays a key role in
arithmetic operations. Adders like Ripple carry adder, Carry look ahead adder, Carry select adder, Carry skip adder and
carry save adder etc. In this paper, a high performance and low power 32bit unsigned multiplier is proposed using adders.
The CLAA based multiplier and CSLA based multiplier uses the same delay for multiplication operation.
SIVASANKAR RAO.Y,SOMASEKHAR .A."SYSTEM EVALUATION OF 32 BIT UNNSIGNED MULTIPLER USING CLAA AND CSLA.". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1236-1239, December - 2015, URL :https://ijcert.org/ems/ijcert_papers/V2I1278.pdf,
Keywords : CLAA,CSLA,Delay,Area, Array Multiplier
 J. Bedrij, “Carry-select adder,” IRE Trans. Electron,
pp. 340–344, 1962.
 B. Rajkumar, .M. Kittur, and P. Kanna, “ASIC
implementation of modified faster carry select adder,”
Eur. J. Sci.Res., vol. 42, no. 1, pp.53–58, 2010.
 Ceiang.T.Y and M. J. Hsiao, “Carry-select adder
using ripple Carry adder,” Electron. Lett, vol. 34, no.
22, pp.2101–2103, Oct. 1998.
 Y. Kim and L.-S. Kim, “carry-select adder with
reduced area,” Electron. Lett. vol. 37, no. 10, pp. 614–
 J. M. Rabaeay, Integrated Circuits—A Design
Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001
 Y. He, C. H. Chang, and J. Gu, “low power & area
efficient 64-bit square Root carry-select adder for low
powerapplications,” in Proc. IEEE Int. Symp.Circuits
Syst., vol. 4, pp. 4082–4085, 2005.
Rado Zlatanovici, Borivoje Nikolic, “Energy-Delay
of Optimization 64-Bit Carry- Lookahead Adders,”
IEEE J.Solid State circuits,vol.44, no. 2, pp. 569-583, Feb.
 Navi.K , Kavehei.O, Rouholamini.M , Sahafi.A,
“Low-Power and High-Performance 1-bit CMOS
Full.Adder Cell,”Journal of Computers, Academy
Press, vol. 3, no. 2,Feb. 2008.
We have kept IJCERT is a free peer-reviewed scientific journal to endorse conservation. We have not put up a paywall to readers, and we do not charge for publishing. But running a monthly journal costs is a lot. While we do have some associates, we still need support to keep the journal flourishing. If our readers help fund it, our future will be more secure.