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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed, Platinum Open Access and Multidisciplinary

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Performance of AHB Bus Tracer with Dynamic Multiresolution and Lossless Real Time Compression

Pursuing M.Tech, VLSI DESIGN, Dept of ECE
Assistant Professor, Department of Electronics and Communication Engineering Avanthi Institute of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India.

In this paper we demonstrate the On-Chip bus SoC(system-on-chip) infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization. The past two decades of SoC evolution have seen an exponential increase in complexity. Today’s devices have multiple processing units, CPUs, GPUs, DSPs, DMAs, third-party IP blocks and custom logic. As if the hardware is not complicated enough, there will of course be substantial amounts of sophisticated software code running on the SoC hardware/software integration, and testing are made very much harder. The commercial consequences of problems in the development flow are potentially dire: since the debugging / analysis needs are adaptable: some designers need all signals at cycle-level, while some others only care about the transactions. For the latter case, tracing all signals at cycle-level wastes a lot of trace memory. Thus, there must be a way to capture traces at different abstraction levels based on the specific debugging/analysis need.

VELLANKI SATHEESH BABU,B.N. SRINIVASA RAO."Performance of AHB Bus Tracer with Dynamic Multiresolution and Lossless Real Time Compression". International Journal of Computer Engineering In Research Trends (IJCERT) ,ISSN:2349-7084 ,Vol.2, Issue 12,pp.1245-1250, December - 2015, URL :,

Keywords : SoC(system-on-chip), bus tracer, On-Chip, SoC debugging and analysis.

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