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International Journal of Computer Engineering in Research Trends. Scholarly, Peer-Reviewed,Open Access and Multidisciplinary
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[1]BalwinderSingh, Arunkhosla and SukhleenBindra "Power Optimization of linear feedback shift register(LFSR) for low power BIST" , 2009 IEEE international Advance computing conference(IACC 2009) Patiala,India 6-7 March 2009. [2]Y.Zorian, "A Distributed BIST control scheme for complex VLSI devices," Proc. VLSI Test Symp., P.4- 9,1993. [3]P.Girard," survey of low-power testing of VLSI circuits," IEEE design and test of computers, Vol. 19,no.3,PP 80-90,May-June 2002. [4]MechrdadNourani,"Low-transition test pattern generation for BIST- Based Applications", IEEE TRANSACTIONS ON COMPUTERS, Vol 57,No.3 ,March 2008. [5]BOYE and Tian-Wang Li," A novel BIST scheme for low power testing," 2010 IEEE. [6]R.S.Katti,X.Y.Ruan , and H.Khattri," MultipleOutput Low-Power Linear feedback shift register design," IEEE Trans.circuitsSyst.I,Vol.53,No.7,pp1487-1495,July 2006. [7]P.Girard, L.Guiller, C.Landrault, S.Pravossoudovitch,andH.J.Wunderlich," A modified clock scheme for a low power BIST test pattern generator," 19th IEEE proc. VLSI test Symp.,CA,pp-306- 311,Apr-May 2001. [8]S.Wang and S.K.Gupta," DS-LFSR: a BIST TPG for low switching activity," IEEE Trans.computer-aided design of Integrated circuits and systems, Vol. 21,No.7,pp.842-851,July 2002. [9]I.Voyiatzis,A.paschalis,D.Nikolos and C.Halatsis, "An efficient built-in self test method for robust path delay fault testing," Journal of electronic testing: Theory and applications Vol.8,No.2,pp-219-222,Apr1996. [10]S.C.Lei, J.Guo, L.Cao, Z.Ye.Liu, and X.M.Wang,"SACSR: A low power BIST method for sequential circuits,: Academic Journal of XI'AN jiaotong university(English Edition),Vol.20,no.3,pp.155- 159,2008. [11]R.H.He,X.W.Li and Y.Z.Gong," A scheme for low power BIST test pattern generator," micro electronics& computer,no.2,pp.36-39 Feb.2003. [12]S.C. Lei, X.Y.Hou ,Z.B.Shao and F.Liang," A class of SIC circuits: theory and application in BIST design," IEEE trans. circuits syst. II, vol.55,no.2,pp.161-165,Feb.2008.
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